275 lines
6.4 KiB
Rust
275 lines
6.4 KiB
Rust
#![no_std]
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#![no_main]
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#![feature(panic_info_message)]
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#![feature(alloc_error_handler)]
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#![feature(naked_functions)]
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#![feature(fn_align)]
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use crate::drivers::{GPU_DEVICE, KEYBOARD_DEVICE, MOUSE_DEVICE};
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extern crate alloc;
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#[macro_use]
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extern crate bitflags;
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#[path = "boards/qemu.rs"]
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mod board;
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use board::*;
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#[macro_use]
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mod console;
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mod config;
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mod drivers;
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mod fs;
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mod gui;
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mod lang_items;
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mod mm;
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mod sbi;
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mod sync;
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mod syscall;
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mod task;
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mod timer;
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mod trap;
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use riscv::register::*;
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// mod riscvreg;
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// use riscvreg::{
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// mstatus, mepc, satp, medeleg, mideleg, sie, mhartid, tp, clint,
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// mscratch, mtvec, mie, sstatus
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// };
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// use riscvregs::registers::*;
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// use riscvregs::registers::pmpcfg0::*;
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//use syscall::create_desktop; //for test
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core::arch::global_asm!(include_str!("entry.asm"));
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fn clear_bss() {
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extern "C" {
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fn sbss();
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fn ebss();
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}
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unsafe {
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core::slice::from_raw_parts_mut(sbss as usize as *mut u8, ebss as usize - sbss as usize)
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.fill(0);
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}
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}
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use lazy_static::*;
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use sync::UPIntrFreeCell;
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lazy_static! {
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pub static ref DEV_NON_BLOCKING_ACCESS: UPIntrFreeCell<bool> =
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unsafe { UPIntrFreeCell::new(false) };
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}
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#[repr(C, align(16))]
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struct Stack([u8; 4096 * 4 * 1]);
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#[no_mangle]
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static mut STACK0: Stack = Stack([0; 4096 * 4 * 1]);
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#[inline]
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pub unsafe fn medeleg_write(medeleg: usize){
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core::arch::asm!("csrw medeleg, {}",in(reg)medeleg);
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}
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pub unsafe fn mideleg_write(mideleg: usize) {
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core::arch::asm!("csrw mideleg, {}", in(reg)mideleg);
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}
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pub enum SIE {
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SEIE = 1 << 9, // external
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STIE = 1 << 5, // timer
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SSIE = 1 << 1, // software
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}
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#[inline]
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pub unsafe fn sie_read() -> usize {
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let ret:usize;
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core::arch::asm!("csrr {}, sie", out(reg)ret);
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ret
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}
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#[inline]
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pub unsafe fn sie_write(x:usize) {
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core::arch::asm!("csrw sie, {}", in(reg)x);
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}
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/// enable all software interrupts
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/// still need to set SIE bit in sstatus
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pub unsafe fn intr_on() {
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let mut sie = sie_read();
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sie |= SIE::SSIE as usize | SIE::STIE as usize | SIE::SEIE as usize;
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sie_write(sie);
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}
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#[no_mangle]
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pub unsafe fn rust_start() -> ! {
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// set MPP mode to Supervisor, for mret
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mstatus::set_mpp(mstatus::MPP::Supervisor);
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// set MEPC to main, for mret
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mepc::write(rust_main as usize);
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// disable paging for now.
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satp::write(0);
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// delegate all interrupts and exceptions to supervisor mode.
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medeleg_write(0xffff);
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mideleg_write(0xffff);
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intr_on();
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// configure Physical Memory Protection to give supervisor mode
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// access to all of physical memory.
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//pmpaddr0::write(0x3fffffffffffff);
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//pmpcfg0::set_pmp(0, Range::TOR, Permission::RWX, false); // 0 < addr < pmpaddr0
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// ask for clock interrupts.
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timer_init();
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// keep each CPU's hartid in its tp register, for cpuid().
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// let id = mhartid::read();
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// core::arch::asm!("mv tp, {0}", in(reg) id);
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// switch to supervisor mode and jump to main().
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core::arch::asm!("mret");
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extern "C" {
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fn rust_main() -> !;
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}
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core::hint::unreachable_unchecked();
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}
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use core::convert::Into;
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use core::ptr;
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// a scratch area per CPU for machine-mode timer interrupts.
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static mut TIMER_SCRATCH: [u64; 5] = [0; 5];
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#[inline]
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unsafe fn read_mtime() -> u64 {
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ptr::read_volatile(Into::<usize>::into(CLINT_MTIME) as *const u64)
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}
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unsafe fn write_mtimecmp(value: u64) {
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let offset = Into::<usize>::into(CLINT_MTIMECMP);
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ptr::write_volatile(offset as *mut u64, value);
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}
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pub unsafe fn add_mtimecmp(interval:u64){
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let value = read_mtime();
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write_mtimecmp(value+interval);
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}
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pub fn count_mtiecmp() -> usize{
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let ret:usize;
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ret = Into::<usize>::into(CLINT) + 0x4000;
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ret
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}
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#[inline]
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pub unsafe fn mtvec_write(x:usize){
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core::arch::asm!("csrw mtvec, {}",in(reg)x);
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}
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use bit_field::BitField;
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#[inline]
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unsafe fn mstatus_read() -> usize {
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let ret:usize;
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core::arch::asm!("csrr {}, mstatus",out(reg)ret);
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ret
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}
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#[inline]
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unsafe fn mstatus_write(x: usize) {
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core::arch::asm!("csrw mstatus, {}",in(reg)x);
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}
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// enable machine-mode interrupts.
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pub unsafe fn mstatus_enable_interrupt(){
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let mut mstatus = mstatus_read();
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mstatus.set_bit(3, true);
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mstatus_write(mstatus);
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}
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pub enum MIE {
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MEIE = 1 << 11, // external
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MTIE = 1 << 7, // timer
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MSIE = 1 << 3 // software
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}
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#[inline]
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pub unsafe fn mie_read() -> usize {
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let ret:usize;
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core::arch::asm!("csrr {}, mie", out(reg)ret);
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ret
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}
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#[inline]
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pub unsafe fn mie_write(x:usize){
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core::arch::asm!("csrw mie, {}",in(reg)x);
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}
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unsafe fn timer_init() {
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// each CPU has a separate source of timer interrupts
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//let id = mhartid::read();
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// ask the CLINT for a timer interrupts
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let interval = 1000000u64; // cycles; about 1/10th second in qemu.
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add_mtimecmp(interval);
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// let mtimecmp = board::clint_mtimecmp(0) as *mut u64;
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// let mtime = board::CLINT_MTIME as *const u64;
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// mtimecmp.write_volatile(mtime.read_volatile() + interval);
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// prepare information in scratch[] for timervec.
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// scratch[0..2] : space for timervec to save registers.
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// scratch[3] : address of CLINT MTIMECMP register.
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// scratch[4] : desired interval (in cycles) between timer interrupts.
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let scratch = &mut TIMER_SCRATCH;
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scratch[3] = count_mtiecmp() as u64;
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scratch[4] = interval;
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mscratch::write(scratch.as_mut_ptr() as usize);
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// set the machine-mode trap handler
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mtvec_write(timervec as usize);
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//mtvec::write(board::timervec as usize, mtvec::TrapMode::Direct);
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// enable machine-mode interrupts.
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mstatus_enable_interrupt();
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//mstatus::set_mie();
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// enable machine-mode timer interrupts.
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mie_write(mie_read() | MIE::MTIE as usize);
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//mie::set_mtimer();
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}
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#[no_mangle]
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pub fn rust_main() -> ! {
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//clear_bss();
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//println!("KERN: begin");
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mm::init();
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loop{};
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//println!("KERN: init gpu");
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//let _gpu = GPU_DEVICE.clone();
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// println!("KERN: init keyboard");
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// let _keyboard = KEYBOARD_DEVICE.clone();
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//println!("KERN: init mouse");
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//let _mouse = MOUSE_DEVICE.clone();
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println!("KERN: init trap");
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trap::init();
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//trap::enable_timer_interrupt();
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//timer::set_next_trigger();
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board::device_init();
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fs::list_apps();
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//gui::init_paint();
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task::add_initproc();
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*DEV_NON_BLOCKING_ACCESS.exclusive_access() = true;
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task::run_tasks();
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panic!("Unreachable in rust_main!");
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}
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